1. Field
The present disclosure relates to a NAND flash memory comprising a current sensing page buffer, and a controlling method thereof. More particularly, but not exclusively, the disclosure relates to a NAND flash memory comprising a current sensing page buffer that is capable of controlling sensing current more precisely and tightly.
2. Description of the Related Art
Among various types of flash memory device, NAND flash memory devices are increasingly used as a high capacity data storage media. Each cell of a flash memory can be programmed to store information by trapping electrons in the cell. The programming operation may be performed, for example, by using the Fowler-Nordheim tunneling effect. A control gate is operatively connected to a word-line of the flash memory, and a voltage is provided to the control gate through the word-line. Each memory cell can be a single level memory cell (SLC), i.e., each cell can store a single bit. Alternatively, each cell may be a multiple level memory cell (MLC), i.e., each cell can store multiple bits. In both SLC and MLC cells, the information stored in each cell is defined by a corresponding threshold voltage of the memory cell.
FIG. 1A is a conceptual block diagram of a conventional NAND flash memory device 100. The flash memory device 100 of this example comprises a memory cell array 20, a page buffer circuit 30, a data input/output (I/O) circuit 40 and a row decoder 10. The memory cell array 20 is operatively connected to the page buffer circuit 30 through a plurality of bit-lines BL and is operatively connected to the row decoder 10 through a plurality of word-lines WL and an additional conductive line (not shown). The additional conductive line may be, for example, a drain selection line or a source selection line for addressing a specific string of the memory cell array. The memory cell array 20 includes a plurality of strings (not shown), each string including a plurality of memory cells. Each memory cell, i.e. the floating gate of each transistor, stores data which may be transferred from the page buffer circuit 30 with the control of the row decoder 10. Stored data in each memory cell may also be transferred to the page buffer circuit 30 with the control of the row decoder 10. Memory cells are arranged at intersections of the plurality of bit-lines BL and the plurality of word-lines WL, respectively.
The page buffer circuit 30 is operatively connected to the memory cell array 20 through the bit-lines BL and is operatively connected to the data input/output circuit 40. The page buffer circuit 30 sets the bit-lines BL during program, read, and erase operations, and senses the data stored in each memory cell of the memory cell array 20 in a read operation. The data input/output circuit 40 is operatively connected to the page buffer circuit 30. The data input/output circuit 40 exchanges data DATA with an external device. The data input/output circuit 40 transfers write data to the page buffer circuit 30 before a writing operation. The data input/output circuit 40 may include components, such as a data buffer and a column pass gate, which are well known in the art.
The row decoder 10 is operatively connected to the memory cell array 20. In operation, the row decoder 10 receives an external address ADDR for selecting any one of the word-lines WL1-WLm. The row decoder 10 is capable of driving the source selection line and the drain selection line of a string to which the addressed cells belong to. The row decoder 10 may apply various voltages, such as a program voltage, a pass voltage, a read voltage, and a ground voltage, to the word-lines WL according to the operation modes.
FIG. 1B is an exemplary block diagram of a memory cell array 20 of the flash memory 100 of FIG. 1A.
The block diagram FIG. 1B is explained herewith for ease of understanding of exemplary conventional structure of NAND flash memory, and not for limiting the invention to this specific scheme. For example, 3D NAND technology may adopt a different scheme than that shown in FIG. 1B.
The memory cell array 20 includes a plurality of blocks 50. Each block 50 includes a plurality of strings 60. Each string includes a plurality of memory cells in which data is stored. Memory cells are arranged at intersections of the plurality of bit-lines BL0˜BLm and the plurality of word-lines WL0˜WLr+k−1, respectively. Strings can be selected or deselected by a drain selection line, e.g. DSL0, DSLj, DSLn, and by a source selection line, e.g. SSL0, SSLj, SSLn. Bit-lines BL0˜BLm of the memory cell array 20 are operatively connected to the page buffer circuit 30 of FIG. 1A. Word-lines WL, drain selection lines DSL and source selection lines SSL are operatively connected to the row decoder 10 of FIG. 1A.
FIG. 1C shows an exemplary structure of respective string and memory cells in the memory cell array of FIG. 1B.
FIG. 1C shows four strings 60. Each string 60 includes a plurality of memory cells 70 in which data is stored, e.g. in the floating gate. In the example of FIG. 1C, one string 60 includes four memory cells 70, but the number of the memory cells included in one string may vary depending on implementation. Memory cells 70 are arranged at intersections of the plurality of bit-lines BL0, BL1 and the plurality of word-lines WL0˜WL7, respectively. Strings can be selected or deselected by controlling the drain selection line, e.g. DSL0, DSL1, and by controlling the source selection line, e.g. SSL0, SSL1. Bit-lines BL0, BL1 of the memory cell array 20 are operatively connected to the page buffer circuit 30 of FIG. 1A. Word-lines WL0˜WL7, drain selection lines DSL0, DSL1 and source selection lines SSL0, SSL1 are operatively connected to the row decoder 10 of FIG. 1A.
The drain selection line DSL0 or DSL1 is operatively connected to the gate of the drain select transistor DST of each string. The source selection line SSL0 or SSL1 is operatively connected to the gate of the source select transistor SST of each string. The source select transistor SST connects each string to the source line SL, and can be switched. To make a specific string be coupled with a corresponding bit-line, high voltage can be driven to the gate of the SST and DST of the string to switch them on. Due to the drain select transistor DST, the source select transistor SST, the source selection line SSL and the drain selection line DSL, specific strings belonging to a same row can be specifically addressed to carry out one of operations such as program, erase, and read operations. The other strings not selected for the operation can be de-coupled from the bit-lines by driving low voltage to the gates of select transistors DST and SST of those strings.
Meanwhile, the architecture of NAND memory devices is driven from market requirements towards the introduction of large size pages together with reduced read latency and improved program throughput. The adoption of an all-bit-line (ABL) scheme has lead to the development of a current sensing scheme suitable to the concurrent reading of all the cells of a physical word-line at the same time, thus providing the considerable advantage of reading all the cells of a physical word-line at the same time and doubling the page size. Being possible to verify all the cells of a word-line concurrently also improved program performances. As a drawback, the current sensing scheme generally adopted in an ABL architecture requires keeping a constant voltage on all the bit-lines, during the whole evaluation and sensing phases with a direct current (DC) path from the bit-lines driving circuitry to the source line through the cells in the on state. As a consequence, the source line cannot be grounded efficiently and cells overdrive is affected by its variation, thus reducing the read current and compromising sensing precision. Various techniques have been introduced to mitigate source rising effect, but the most effective among them present the drawback of requiring at least two subsequent readings and increasing read time. Another issue which may arise is related to the noise generated inside sensing circuitry when all the cells of a page are sensed in parallel.
FIG. 2A shows a circuit diagram illustrating a conventional page buffer circuit 30 suitable to perform a current sensing.
The page buffer circuit 30 for a NAND flash memory comprises a first node CSO, an NMOS transistor M1 arranged between the first node CSO and a corresponding bit-line BL, an NMOS transistor M5, a sensing node SEN, a NMOS transistor M2 arranged between the first node CSO and the sensing node SEN, a transistor M4 configured to provide a pre-charging path to the bit-line BL through the first node CSO and the NMOS transistor M1 from a first voltage source VCORE. The page buffer circuit 30 further comprises the first voltage source VCORE, and a second voltage source VDC_PB.
The page buffer circuit 30 further comprises a PMOS transistor M6 coupled with the sensing node SEN and configured to switch the path from the second voltage source VDC_PB to a sense latch 31. The sense latch 31 is configured to receive at its input QS a drain voltage of the PMOS transistor M6. The input QS of the sense latch 31 is operatively connected to the gates of transistors M7 and M9 to enable or disable the current path from the first and second voltage sources, VCORE and VDC_PB, to each of the transistors M2, M4, M5 based on the voltage of the input QS of the sense latch 31.
The operation of the page buffer circuit 30 will be explained in reference to FIG. 2A and FIG. 2B. FIG. 2B shows a timing diagram of the page buffer circuit 30 of FIG. 2A performing a current sensing.
First, the sense latch 31 is reset so that the input QS is low, then all bit-lines BLs are pre-charged at the same time by rising a voltage PB_SENSE to the desired bit-line level plus a threshold in a pre-charge period t1. Pre-charge path is powered through the PMOS transistor M7, and the NMOS transistor M4 whose gate voltage is controlled to a desired voltage, e.g., 2V. These voltages are applied for a time sufficient to pre-charge the bit-lines, i.e. during the pre-charge period t1. The nodes CSO and SEN are isolated one from each other, and the pre-charge voltage of the node CSO is controlled to be equal to the voltage CSO_PRECH minus a threshold. Before the pre-charge period t1 ends, also the voltages SA_CSOC, SA_SENSE and SA_PRECH_N are enabled. The voltage SA_CSOC is driven to a voltage a bit higher than the voltage PB_SENSE, e.g., 1.4V, and SA_SENSE is driven to a voltage a bit higher than the voltage SA_CSOC, e.g., 1.55V.
While the pre-charge voltage of the node CSO is tightly controlled to a desired voltage by means of the CSO_PRECH transistor, M4, the node SEN is pre-charged to the voltage VDC_PB. Before the evaluation phase, the SA_DISCH transistor M11 is disabled.
A first evaluation period t2 starts when the CSO_PRECH voltage is grounded, and the voltage SA_PRECH_N, i.e., the gate of the transistor M7, rises to VDC_PB. The node CSO is now floating and eventually discharged by the current sunk from the cell. When it reaches the voltage SA_SENSE minus a threshold, the transistor M2 having the gate coupled to the voltage SA_SENSE turns on and the node SEN is discharged to the voltage of the node CSO. In the first evaluation period t2, the voltage SA_CSOC ensures that the node CSO is not discharged below an initial bit-line voltage plus a delta. As a consequence the bit-line voltage is kept constant and the bit-line to bit-line interference is suppressed.
After the first evaluation period t2, the strobe signal, i.e., SA_STB_N, is enabled. If the node SEN has been discharged, the PMOS transistor M6 is enabled and the input QS goes high, otherwise the latch data is maintained. When the strobe pulse of the voltage SA_STB_N ends, the voltages SA_SENSE, SA_CSOC, PB_SENSE are raised to a higher voltage, i.e., +ΔV2, and the voltages SA_PRECH_N and SA_DISCH are reasserted during a recovery period t4.
During the read sequence just described above, the cells are all enabled in parallel and the voltage of the bit-lines BL is kept constant. The huge current sunk from the bit-line driving circuitry to the cells through common source line SL causes it to rise of a few hundred mV so that the gate-to-source voltage of the cells is reduced. This phenomenon results in a lower cell current and can reduce the read margin of the erased cells. Due to this effect, the reading is repeated in safer conditions. After the first reading including the pre-charge period t1, the first evaluation period t2, and the first strobe period t3, the sense latch 31 of the page buffer unit 30 with high read current is flipped to have the input QS high, and the pre-charge path to the bit-line BL is prevented by the transistors M7 and M9.
A discharge path is enabled through the transistors M11 and M12 having the gate coupled to the voltage SA_DISCH which is disabled during the first sensing phase t1˜t3, but re-activated thereafter. The bit-lines BLs operatively connected to the cell with high current are discharged, while others are pre-charged again if eventually coupled down by adjacent bit-lines BLs under discharge. The page buffer control voltages PB_SENSE are raised to higher level, e.g., +200 mV, in order to have higher BL voltage and, after the recovery period t4, a second evaluation period t5 and a second strobe period t6 are repeated.
The bit-line BL is pre-charged with the transistor M1 having its gate biased by the voltage PB_SENSE and its sub-threshold leakage can compromise the reading. In other words, during the pre-charge period t1, the gate voltage of the transistor M1, i.e., PB_SENSE, is kept constant, but the source voltage of the transistor M1 rises. The pre-charge of the bit-line BL is very slow due to the current reduction of the transistor M1 during the last part of the transient, caused by the reduced difference between the gate and source voltages. The last part of the bit-line pre-charge is actually performed with the transistor M1 in the cut-off region, which causes a sub-threshold leakage.
For this reason, the recovery period t4 should be long enough, e.g., up to 10 μs, which significantly increases the reading duration.
The introduction of two subsequent readings, however, solves another issue related to the commutation noise produced by the sensing of all cells of the page in parallel. Since the nodes CSO of the page buffers with erased cells are discharged during the evaluation period, the parasitic capacitance of the transistors can couple down the analog control signals, such as PB_SENSE, SA_CSOC and SA_SENSE. Since the evaluation time (t2+t3) is very short and more time is required for the recoveries of the voltages of the analog control signals, the drop on these lines can affect the sensing precision significantly. On second reading, the number of erased cells still under reading is dramatically reduced and this drop becomes negligible, thus proving a more stable and precise reading.
As the program operation, an incremental step pulse programming (ISPP) technique is usually used, which is well adapted for use with a range of threshold voltages defining multiple programming states for a MLC.
After every program pulse, a program verify operation is performed to check if the cells are programmed at a required Vth level. The program verify operation is a read operation. In MLC and TLC, the number of levels to be programmed is 4 and 8 respectively, so the program verify operation needs to be performed 3 or 7 times after every program pulse. ISPP with all verify operations will continue until all levels are verified correctly, so that the program time is strongly dependant on the program verify time inducing a program throughput issue. Moreover, in prior art, a common program technique includes the double verification for each distribution under program in order to apply a program pulse with reduced efficiency after verification, when cells have been programmed not to the final verify value, but close to and slight lower than the final verify value. This is a time consuming operation which will be addressed in the following for program time reduction.